1. Field of The Invention
The present invention relates generally to equilibration circuitry for a data bus, and more specifically, to a method and apparatus for equilibration of a single ended data bus.
2. Description of The Related Art
In memory devices, such as dynamic random access memory (DRAM) devices, buses are used as communications pathways linking together various modules of the system. Typically these buses include the data bus, the address bus, and the control bus. The data bus is used to transfer data. System-wide control and timing signals are required to synchronize the operation of the separate and different modules of the memory device, and facilitate their intercommunication activities over the buses. Usually a microprocessor is in control of these buses either directly or through a bus controller and the timing of events on the buses is very important.
Data on the data bus gets latched or stored. During a new data sense time the bus is driven to a known voltage level which facilitates faster data transitions, once the new data arrives. Driving a data bus line to a known voltage level can be done with an equilibration signal used to ramp up the voltage. Typically, a separate equilibration circuit is coupled to the memory device to provide an equilibration signal. This equilibration signal attempts to equalize the voltage levels on complementary pairs of input/output lines in the memory device.
FIG. 1 shows an example of a prior art data bus line system 10 for a memory device having a memory array 20 with array output drivers 21, 22, 23, 24 that supply data signals on respective data bus lines 31, 32, 33, 34. Each data bus line 31, 32, 33, 34 has a corresponding register 41, 42, 43, 44 and corresponding output pad 51, 52, 53, 54. A clock register signal CLKREG is used to load data into each register 41, 42, 43, 44. Each register 41, 42, 43, 44 typically contains a latch and an output driver. The data bus line system 10 also has an additional register 61 and a driver 71 connected to the first data bus line 31 to provide a data feedback to the array 20.
FIG. 2 is a schematic representation of the prior art system of FIG. 1 showing some of the components of the array 20. The array 20 contains an array core 25, a sense amplifier 26, a latch 27, and an array driver 21. A data sense amplifier clock signal CLKDSA is used to operate the sense amplifier 26.
In a conventional system, such as that depicted in FIGS. 1 and 2, the data bus lines are relatively short for a given memory density. As the memory densities have become larger, however, the data bus lines have become relatively longer. Unfortunately, as data bus lines get longer, the operational speed of the memory device is reduced. Some conventional memory devices also include data bus lines having a pair of complementary output lines (commonly referred to as a dual ended data bus line). The dual ended data bus lines require more die size because of the large number of output lines and for this reason the industry preference is for a single ended data output.
Accordingly, there is a desire and need for a single ended data bus line with improved speed characteristics for use in high density memory devices.
The above mentioned problems are addressed by the present invention which incorporates a unique equilibration circuit for driving a bus line which may be used to output memory array data, address data or command data. In particular, the present invention provides an equilibration circuit that precharges the voltage of the data bus line to allow for faster recognition and latching of output data placed on the data bus line. The equilibration circuit precharges the data bus line to a voltage which is substantially midway of the logic signal voltage levels used to output data on the line.
Other features and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.